1. Field of the Invention
The present invention relates to a method for fabricating a so-called PN-isolated flat-cell semiconductor memory device. In the device, a conductive impurity of a second type is ion-doped into regions, other than the channel region, between the source and conductive drain diffusion layers of a first type in a cell transistor, thereby isolating the elements.
2. Description of the Related Art
In general, a device of the flat-cell type is available for improving the pattern density of a semiconductor memory device.
In such a ROM (Read Only Memory) of the flat-cell type, an isolation method such as LOCOS (Local Oxidation of Silicon) or trench isolation is not used for element isolation but PN isolation is used therefore. In the PN isolation, an element isolation region is formed by ion-doping a P-type impurity into a region other than the channel region between the N-type diffusion layers in which the source and drain of a cell transistor may be eventually formed.
FIG. 1 is a plan view showing a conventional flat-cell semiconductor memory device. FIGS.2A to 2C are cross-sectional views showing a method for fabricating the device in the order of the steps to be followed. In these drawings, metal traces are not illustrated. Incidentally, FIGS. 2A to 2C are cross-sectional views taken along line A--A of FIG. 1 (For example, Publication of Japanese Patent No.2561071).
As shown in FIG. 1, a plurality of N.sup.+ diffusion layers 111, parallel to one another, which will serve as the source and drain regions of a memory transistor, are formed on a semiconductor substrate. In addition, a plurality of word lines 112 are formed, parallel to one another, orthogonal to and in transverse relation to the N.sup.+ diffusion layers 111 via a gate insulating film. P-type impurity regions 115 are formed at regions other than the N.sup.+ diffusion layers 111 and those covered with the word lines 112, thereby isolating the memory transistors from one another. Incidentally, the spacing between adjacent N.sup.+ diffusion layers 111 is the length of the gate (the channel length) 113 and the width of a word line 112 is the width of the gate (the channel width) 114.
Next, a method for fabricating the memory semiconductor device will be explained. First, an insulating film is formed on a semiconductor substrate 101 and then ion is implanted for threshold control via the insulating film. Thereafter, an N-type impurity is ion-doped into the semiconductor substrate 101 to form the N.sup.+ diffusion layers 111 by employing a photo resist as a mask with openings provided for the regions in which the N.sup.+ diffusion layers 111 shown in FIG. 1 will be eventually formed.
Then, as shown in FIG. 2A, a gate oxide film 102 is formed on the semiconductor substrate 101. Moreover, a polysilicon layer is formed on the gate oxide film 102. Then, a resist pattern is formed on the polysilicon layer by photolithography and etching is performed using the photo resist pattern as a mask, thereby forming gate electrodes 103 which will eventually serve as the word lines 112.
Then, as shown in FIG. 2B, a P-type impurity 104 is ion-doped into the entire surface for the purpose of element isolation. At this time, the P-type impurity 104 is ion-doped into the N.sup.+ diffusion layers 111. However, the dose of the N.sup.+ diffusion layers 111 is about two orders of magnitude greater than that of the ion implantation of the P-type impurity for element isolation. Therefore, the N.sup.+ diffusion layers 111 remain as N-type layers. Thus, only the regions where the word lines 112 are not formed become P-type impurity regions 105, except the N.sup.+ diffusion layers 111. That is, this technique provides element isolation for the N.sup.+ diffusion layers 111 and the word lines 112 by self-alignment.
Next, as shown in FIG. 2C, thermal processing performed to activate the P-type impurity causes the P-type impurity regions to diffuse to turn the P-type impurity regions 105 into element isolating P-type impurity regions 105a. A memory semiconductor device fabricated as such has the word lines and the bit lines made up of diffusion layers in transverse relation to each other. This eliminates the need to provide each of the bit lines with contacts for metallization, thereby improving the pattern density.
However, according to this conventional method f or fabricating a semiconductor memory device, the ion implantation of the P-type impurity 104 for element isolation is performed immediately after the formation of the word lines that serve also as the gate electrodes. Accordingly, as shown in FIG. 2C, thermal processing performed to activate the P-type impurity ions causes the element isolating P-type impurity regions 105a to diffuse so as to narrow the spacing between adjacent regions. That is, this presents a problem that the regions diffuse to narrow the effective channel width (the gate width) in the flat cell, thereby reducing cell currents.
In addition, this presents another problem that reducing the dose of the P-type impurity ions to ensure cell currents causes leak currents between the diffusion layers to increase to provide a narrowed margin of circuit operation.